1. Field of the Invention
Example embodiments of the present invention may relate to a multi-chip package, and more particularly, to a multi-chip package having a stacked plurality of different sized semiconductor chips.
2. Description of the Related Art
In response to recent developments in the semiconductor industry and increased user demands, electronic devices are getting smaller and lighter. Therefore, semiconductor chip packages, which may be considered the core component of an electronic device, are also getting smaller and lighter. In this regard, a stacked chip package, in which a plurality of semiconductor chips are vertically stacked on a mounting substrate, and a wafer level package, in which semiconductor chips are separated into individual devices after they are package in a wafer, have been proposed. The stacked semiconductor chip package and the wafer level package significantly contribute to the reduction in size, weight, and mounting area at a higher extent than in the case of a single chip package having a single semiconductor chip.
Also, the rapid development in mobile products is increasing the demand for a system-in-package (SIP) and a multi-chip package (MCP) in which various types of semiconductor devices, for example, a DRAM, an SRAM, a flash memory, and a CPU may be stacked on a substrate.
The MCP may be stacked with different types of semiconductor chips, each of the semiconductor chips having different sizes; therefore, it is not possible to manufacture the MCP at a wafer level. However, it is possible to manufacture a multi-chip package at a chip level. The semiconductor chips should be connected to a printed circuit board by wire bonding, because pad locations on each of the semiconductor chips may be different.
When using bonding wires, for example, stack wires, a minimum interval space between the wires should be maintained, and a printed circuit board should also have a minimum area in order to prevent insulation problems and/or crosstalk between the wires. Therefore, a package employing the bonding wires generally has a larger size than that of a wafer level package.